--http://esd.cs.ucr.edu/labs/tutorial/register.vhd
---------------------------------------------------
--n-bit Register(ESD book figure 2.6)
--by Weijun Zhang,04/2001
--
--KEY WORD:concurrent,generic and range
---------------------------------------------------
 
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity w2MEruC5TqdipJ7WkaWfaP1knepod13e is generic(aKYRcQ7Ky4zYeTTHYfjILYNcNQPsTJNg:natural:=2);port(fFKOPhlhgo9kArIhWQAOeHvA1F6bNbHr:in std_logic_vector(aKYRcQ7Ky4zYeTTHYfjILYNcNQPsTJNg-1 downto 0);yMMJxs1tjip05affrPninll0gWddJ8ZY:in std_logic;Hu08QQzhtPz1MWer9ir10kZuCuy9Hiu8:in std_logic;GGfNHVyvxlWdUvWkI7iEiocAVVzLPLle:in std_logic;yNv5IzVxcKyjouVveBYEs07Hk29J0EiB:out std_logic_vector(aKYRcQ7Ky4zYeTTHYfjILYNcNQPsTJNg-1 downto 0));end w2MEruC5TqdipJ7WkaWfaP1knepod13e;architecture rdH3SIfeP8SEtWnzmHfAfv9QVTcNeATw of w2MEruC5TqdipJ7WkaWfaP1knepod13e is signal cAaLpYzMKBRBaPTUoy0HNntF9iMkHwj7:std_logic_vector(aKYRcQ7Ky4zYeTTHYfjILYNcNQPsTJNg-1 downto 0);begin process(fFKOPhlhgo9kArIhWQAOeHvA1F6bNbHr,yMMJxs1tjip05affrPninll0gWddJ8ZY,Hu08QQzhtPz1MWer9ir10kZuCuy9Hiu8,GGfNHVyvxlWdUvWkI7iEiocAVVzLPLle)begin if GGfNHVyvxlWdUvWkI7iEiocAVVzLPLle='0'then cAaLpYzMKBRBaPTUoy0HNntF9iMkHwj7<=(cAaLpYzMKBRBaPTUoy0HNntF9iMkHwj7'range=>'0');elsif(yMMJxs1tjip05affrPninll0gWddJ8ZY='1'and yMMJxs1tjip05affrPninll0gWddJ8ZY'event)then if Hu08QQzhtPz1MWer9ir10kZuCuy9Hiu8='1'then cAaLpYzMKBRBaPTUoy0HNntF9iMkHwj7<=fFKOPhlhgo9kArIhWQAOeHvA1F6bNbHr;end if;end if;end process;yNv5IzVxcKyjouVveBYEs07Hk29J0EiB<=cAaLpYzMKBRBaPTUoy0HNntF9iMkHwj7;end rdH3SIfeP8SEtWnzmHfAfv9QVTcNeATw;